1. Field of the Invention
The present invention relates to an information processing apparatus and an information processing method that create an environment for emulation by using a verification model in logic circuit design.
2. Description of the Related Art
In the logic circuit design, the behavior of a designed logic circuit needs to be verified. Hardware used for verification includes a reconfigurable logic integrated circuit (IC) and a hardware emulator configured by a specific central processing unit (CPU) (hereinafter, a hardware emulator will be denoted simply as an emulator).
If the method of verifying behavior by supplying prepared input data to a verification target is used, as illustrated in FIG. 2A, a circuit of a verification target 114 is arranged on the side of an emulator. Also, a verification model 113 is mounted on a computer (hereinafter, referred to as a PC) as a program. Then, input data 103 is transferred from the PC to the verification target 114 on the side of the emulator.
However, when emulating processing in which a large-capacity image is input as input data, data transfer from the PC to the emulator occurs by unit of clock events of emulation and thus, the speed of emulation is controlled by communication between the PC and emulator.
Thus, as illustrated in FIG. 2B, a method by which the verification model 113 and a memory 112 are arranged on the emulator side together with the verification target 114 and a memory data transfer unit 111 is implemented on the PC side as a program is known. At first, according to this method, the memory data transfer unit 111 on the PC side transfers the input data 103 to the memory 112 playing the role of a buffer on the emulator side. Next, the verification model 113 supplies data in the memory 112 to the verification target 114.
By using this method, the memory data transfer unit 111 on the PC side can collectively transfer, to the emulator, the input data 103 corresponding to the capacity of the memory 112 playing the role of a buffer. In other words, the communication from the PC to the emulator by unit of clock events is not needed, so that the verification can be made faster.
To build a high-speed emulation environment as illustrated in FIG. 2B, it is necessary to design the verification model 113 in a register transfer level (RTL) hardware description language. In recent years, a design method in which a logic circuit is designed at a high level of abstraction and then RTL is generated by behavioral synthesis is adopted. According to this method, a behavioral description realizing a desired behavior of a logic circuit is designed and the behavioral description is converted into RTL by using behavioral synthesis tools.
Moreover, it is necessary to perform verification to check whether the designed behavioral description implements the desired behavior correctly. A verification program used for verification of the behavioral description is designed in a behavioral description at a high level of abstraction of the C language or the like.
Thus, a method of implementing the verification program on the emulator by behavioral synthesis can be considered. To verify supplying input data prepared as a file to the verification target, the verification program has a description of file input/output. A file pointer is specific to software and does not exist in hardware and thus, behavioral synthesis cannot be performed directly.
Japanese Patent Application Laid-Open No. 2005-78402 enables behavioral synthesis of a verification program designed with a behavioral description having a description of file input/output. If the behavioral synthesis is applied, a description of a file function in the verification program is converted into a verification model described in a hardware description language that does not allow logic synthesis.
A verification model containing a file function generated by the method discussed in Japanese Patent Application Laid-Open No. 2005-78402 does not allow logic synthesis and logic synthesis cannot be used when implemented on a PC, imposing heavy loads on the user. Also, according to the method discussed in Japanese Patent Application Laid-Open No. 2005-78402, the memory 112 playing the role of a buffer does not exist and thus, like the configuration in FIG. 2A, a high-speed emulation environment cannot be realized.
Thus, as described above, design based on logic synthesis cannot be used to build a high-speed emulation environment including a behavior of file input/output and therefore, heavy loads are imposed on the user.